Bypass capacitors are commonly used with modern integrated circuit ("IC") "chips" to reduce the noise in the power supplied to the chips. Advances in IC technology have dramatically increased the switching speeds employed by the newest generation of IC devices, so that many new chips are capable of operation at microwave frequencies. High switching speeds increase the problem of power supply noise, a component of which is generated as the device is switched on and off. In order for IC chips to function properly, the power supplied must be relatively "clean", i.e., free from noise.
Use of bypass capacitors to alleviate power supply noise problems is well known. It is also well known that it is desirable to position the bypass capacitor as close as possible to the chip for best effect. The leads connecting the capacitor to the chip have an inherent inductance which becomes significant at high speed operation, to the point that if the capacitor is positioned too far from the chip, the lead inductance can cancel the usefulness of the capacitor for eliminating power supply noise. The maximum tolerable distance between the bypass capacitor and the chip is a function of the lead diameter (and, hence, inductance) and the frequency of chip operation. As device geometries shrink so have lead diameters. Thus, at high frequency operation, it has become increasingly important to minimize the lead length by moving the capacitor as close as possible to the chip.
Prior art methods of accomplishing this include mounting a discrete capacitor on or near the IC chip, or forming a capacitor on or as part of the carrier substrate used to hold the chip and to interconnect it to the "outside" world.
Various methods are available for connecting IC chips to other devices. Connections are required not only for power supply, but also for signal lines between chips, other device components and various input/output ("I/O") devices. One class of interconnect methods involve so-called "flip-chip" bonding in which the active surface of the IC chip is mounted in opposing relationship onto a carrier substrate. Flip-chip bonding has the advantage of providing a relatively high density of connections in a small area. For convenience, a chip mounted on a carrier substrate will be referred to as a chip module.
The most common interconnect technology associated with flip-chip bonding involves the use of solder bumps. Typically, arrays of opposing solder bumps are formed on both the active surface of the chip and the carrier substrate. The solder is melted or "reflowed" and the arrays are brought into alignment so that connection is made. As the solder hardens, solder posts are formed between the chip and the substrate. This technique is often referred to in the literature as "C4" (or "C.sup.4 ") technology. Other interconnect techniques used in connection with flip-chip bonding include the use of wire interconnect posts formed on one or the other of the substrates (i.e., either the chip or, more commonly, the carrier) and then joined to connection pads on the other, for example, by soldering.
As IC device densities have increased the number of required interconnections has increased while the space available for the interconnections has decreased. As noted, this has encouraged increased use of flip-chip bonding technologies. The result of these greater device densities is also that the real estate available both on the chip and on (or within) the carrier substrate has become increasingly more valuable. Since signal and power supply routing is frequently accomplished through the carrier substrate, increasing the number of signal lines increases the complexity of the carrier substrate. Carder substrates are typically multilayer structures fabricated using known ceramic or copper/polyimide technologies. While the traditional approach to handling the greater complexity has been to add more layers to the carrier substrate, there are limits to the number of layers that can be used. Adding layers results in reduced product yields, which is undesirable. Likewise, adding fabrication steps results in lower yields.
Accordingly, there is a need for a power supply bypass capacitor which is easy to form and which can be positioned quite close to an IC chip without taking up valuable real estate on the chip or on the carrier substrate.
Therefore, an object of the present invention is to provide a novel bypass capacitor which is positioned in close proximity to an integrated circuit chip.
Another object of the present invention is to provide a bypass capacitor which takes up only minimal real estate on the surface of the chip and on the surface of the chip carrier.
Another object of the present invention is to provide a bypass capacitor that is relatively easy to form, so that yields of chip modules are increased.